Type Alias ClkbiasdisW 

pub type ClkbiasdisW<'a, REG> = BitWriter<'a, REG, Clkbiasdis>;

Field CLKBIASDIS writer - Clock Bias Disable Bit

Aliased Type

pub struct ClkbiasdisW<'a, REG> { /* private fields */ }

Implementations

impl<'a, REG> ClkbiasdisW<'a, REG>

where REG: Writable + RegisterSpec,

pub fn _0(self) -> &'a mut W<REG>

No effect

pub fn _1(self) -> &'a mut W<REG>

In VLPS mode, the bias currents and reference voltages for the following clock modules are disabled: SIRC, FIRC, PLL. (if available on device)