Enum Clkbiasdis 

pub enum Clkbiasdis {
    _0 = 0,
    _1 = 1,
}

Clock Bias Disable Bit

Value on reset: 0

Variants

_0 = 0

0: No effect

_1 = 1

1: In VLPS mode, the bias currents and reference voltages for the following clock modules are disabled: SIRC, FIRC, PLL. (if available on device)

Trait Implementations

impl Clone for Clkbiasdis

fn clone(&self) -> Clkbiasdis

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Clkbiasdis

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Format for Clkbiasdis

fn format(&self, f: Formatter<'_>)

Writes the defmt representation of self to fmt.

impl From<Clkbiasdis> for bool

fn from(variant: Clkbiasdis) -> Self

Converts to this type from the input type.

impl PartialEq for Clkbiasdis

fn eq(&self, other: &Clkbiasdis) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Clkbiasdis

impl Eq for Clkbiasdis

impl StructuralPartialEq for Clkbiasdis