Crate s32k142_pac

Crate s32k142_pac 

Expand description

Peripheral access API for S32K142 microcontrollers (generated using svd2rust v0.37.0 (a5d3538 2025-09-26))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports§

pub use self::Interrupt as interrupt;rt
pub use self::ftm0 as ftm1;
pub use self::ftm0 as ftm2;
pub use self::ftm0 as ftm3;
pub use self::adc0 as adc1;
pub use self::lpspi0 as lpspi1;
pub use self::lpuart0 as lpuart1;
pub use self::pta as ptb;
pub use self::pta as ptc;
pub use self::pta as ptd;
pub use self::pta as pte;

Modules§

adc0
Analog-to-Digital Converter
aips
AIPS-Lite Bridge
can0
Flex Controller Area Network module
can1
Flex Controller Area Network module
cmp0
High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
crc
Cyclic Redundancy Check
cse_pram
CSE_PRAM
dma
Enhanced Direct Memory Access
dmamux
DMA channel multiplexor
eim
Error Injection Module
erm
ERM
ewm
External Watchdog Monitor
flexio
The FLEXIO Memory Map/Register Definition can be found here.
ftfc
FTFC
ftm0
FlexTimer Module
generic
Common register and bit access and modify traits
lmem
Local Memory Controller
lpi2c0
The LPI2C Memory Map/Register Definition can be found here.
lpit0
Low Power Periodic Interrupt Timer (LPIT)
lpspi0
The LPSPI Memory Map/Register Definition can be found here.
lptmr0
Low Power Timer
lpuart0
Universal Asynchronous Receiver/Transmitter
mcm
Core Platform Miscellaneous Control Module
mscm
MSCM
pcc
PCC
pdb0
Programmable Delay Block
pdb1
Programmable Delay Block
pmc
PMC
porta
Pin Control and Interrupts
portb
Pin Control and Interrupts
portc
Pin Control and Interrupts
portd
Pin Control and Interrupts
porte
Pin Control and Interrupts
pta
General Purpose Input/Output
rcm
Reset Control Module
rtc
Secure Real Time Clock
s32_nvic
Nested Vectored Interrupt Controller
s32_scb
System Control Registers
s32_sys_tick
System timer
scg
System Clock Generator
sim
System Integration Module
smc
System Mode Controller
trgmux
TRGMUX
wdog
Watchdog timer

Structs§

CBP
Cache and branch predictor maintenance operations
CPUID
CPUID
CorePeripherals
Core peripherals
DCB
Debug Control Block
DWT
Data Watchpoint and Trace unit
FPB
Flash Patch and Breakpoint unit
FPU
Floating Point Unit
ITM
Instrumentation Trace Macrocell
MPU
Memory Protection Unit
NVIC
Nested Vector Interrupt Controller
Peripherals
All the peripherals.
SCB
System Control Block
SYST
SysTick: System Timer
TPIU
Trace Port Interface Unit

Enums§

Interrupt
Enumeration of all the interrupts.

Constants§

NVIC_PRIO_BITS
Number available in the NVIC for configuring priority

Statics§

DEVICE_PERIPHERALS 🔒

Functions§

ADC0 🔒 ⚠
ADC1 🔒 ⚠
CAN0_Error 🔒 ⚠
CAN0_ORed 🔒 ⚠
CAN0_ORed_0_15_MB 🔒 ⚠
CAN0_ORed_16_31_MB 🔒 ⚠
CAN0_Wake_Up 🔒 ⚠
CAN1_Error 🔒 ⚠
CAN1_ORed 🔒 ⚠
CAN1_ORed_0_15_MB 🔒 ⚠
CMP0 🔒 ⚠
DMA0 🔒 ⚠
DMA1 🔒 ⚠
DMA2 🔒 ⚠
DMA3 🔒 ⚠
DMA4 🔒 ⚠
DMA5 🔒 ⚠
DMA6 🔒 ⚠
DMA7 🔒 ⚠
DMA8 🔒 ⚠
DMA9 🔒 ⚠
DMA10 🔒 ⚠
DMA11 🔒 ⚠
DMA12 🔒 ⚠
DMA13 🔒 ⚠
DMA14 🔒 ⚠
DMA15 🔒 ⚠
DMA_Error 🔒 ⚠
ERM_double_fault 🔒 ⚠
ERM_single_fault 🔒 ⚠
FLEXIO 🔒 ⚠
FTFC 🔒 ⚠
FTFC_Fault 🔒 ⚠
FTM0_Ch0_Ch1 🔒 ⚠
FTM0_Ch2_Ch3 🔒 ⚠
FTM0_Ch4_Ch5 🔒 ⚠
FTM0_Ch6_Ch7 🔒 ⚠
FTM0_Fault 🔒 ⚠
FTM0_Ovf_Reload 🔒 ⚠
FTM1_Ch0_Ch1 🔒 ⚠
FTM1_Ch2_Ch3 🔒 ⚠
FTM1_Ch4_Ch5 🔒 ⚠
FTM1_Ch6_Ch7 🔒 ⚠
FTM1_Fault 🔒 ⚠
FTM1_Ovf_Reload 🔒 ⚠
FTM2_Ch0_Ch1 🔒 ⚠
FTM2_Ch2_Ch3 🔒 ⚠
FTM2_Ch4_Ch5 🔒 ⚠
FTM2_Ch6_Ch7 🔒 ⚠
FTM2_Fault 🔒 ⚠
FTM2_Ovf_Reload 🔒 ⚠
FTM3_Ch0_Ch1 🔒 ⚠
FTM3_Ch2_Ch3 🔒 ⚠
FTM3_Ch4_Ch5 🔒 ⚠
FTM3_Ch6_Ch7 🔒 ⚠
FTM3_Fault 🔒 ⚠
FTM3_Ovf_Reload 🔒 ⚠
LPI2C0_Master 🔒 ⚠
LPI2C0_Slave 🔒 ⚠
LPIT0_Ch0 🔒 ⚠
LPIT0_Ch1 🔒 ⚠
LPIT0_Ch2 🔒 ⚠
LPIT0_Ch3 🔒 ⚠
LPSPI0 🔒 ⚠
LPSPI1 🔒 ⚠
LPTMR0 🔒 ⚠
LPUART0_RxTx 🔒 ⚠
LPUART1_RxTx 🔒 ⚠
LVD_LVW 🔒 ⚠
MCM 🔒 ⚠
PDB0 🔒 ⚠
PDB1 🔒 ⚠
PORTA 🔒 ⚠
PORTB 🔒 ⚠
PORTC 🔒 ⚠
PORTD 🔒 ⚠
PORTE 🔒 ⚠
RCM 🔒 ⚠
RTC 🔒 ⚠
RTC_Seconds 🔒 ⚠
Read_Collision 🔒 ⚠
SCG 🔒 ⚠
SWI 🔒 ⚠
WDOG_EWM 🔒 ⚠

Type Aliases§

Adc0
Analog-to-Digital Converter
Adc1
Analog-to-Digital Converter
Aips
AIPS-Lite Bridge
Can0
Flex Controller Area Network module
Can1
Flex Controller Area Network module
Cmp0
High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
Crc
Cyclic Redundancy Check
CsePram
CSE_PRAM
Dma
Enhanced Direct Memory Access
Dmamux
DMA channel multiplexor
Eim
Error Injection Module
Erm
ERM
Ewm
External Watchdog Monitor
Flexio
The FLEXIO Memory Map/Register Definition can be found here.
Ftfc
FTFC
Ftm0
FlexTimer Module
Ftm1
FlexTimer Module
Ftm2
FlexTimer Module
Ftm3
FlexTimer Module
Lmem
Local Memory Controller
Lpi2c0
The LPI2C Memory Map/Register Definition can be found here.
Lpit0
Low Power Periodic Interrupt Timer (LPIT)
Lpspi0
The LPSPI Memory Map/Register Definition can be found here.
Lpspi1
The LPSPI Memory Map/Register Definition can be found here.
Lptmr0
Low Power Timer
Lpuart0
Universal Asynchronous Receiver/Transmitter
Lpuart1
Universal Asynchronous Receiver/Transmitter
Mcm
Core Platform Miscellaneous Control Module
Mscm
MSCM
Pcc
PCC
Pdb0
Programmable Delay Block
Pdb1
Programmable Delay Block
Pmc
PMC
Porta
Pin Control and Interrupts
Portb
Pin Control and Interrupts
Portc
Pin Control and Interrupts
Portd
Pin Control and Interrupts
Porte
Pin Control and Interrupts
Pta
General Purpose Input/Output
Ptb
General Purpose Input/Output
Ptc
General Purpose Input/Output
Ptd
General Purpose Input/Output
Pte
General Purpose Input/Output
Rcm
Reset Control Module
Rtc
Secure Real Time Clock
S32Nvic
Nested Vectored Interrupt Controller
S32Scb
System Control Registers
S32SysTick
System timer
Scg
System Clock Generator
Sim
System Integration Module
Smc
System Mode Controller
Trgmux
TRGMUX
Wdog
Watchdog timer

Attribute Macros§

interruptrt