PDB channel’s corresponding pre-trigger is in bypassed mode. The
pre-trigger asserts one peripheral clock cycle after a rising edge is
detected on selected trigger input source or software trigger is
selected and SWTRIG is written with 1.
PDB channel’s corresponding pre-trigger asserts when the counter reaches
the channel delay register and one peripheral clock cycle after a rising
edge is detected on selected trigger input source or software trigger is
selected and SWTRIG is written with 1.