Type Alias W 

pub type W = W<BaudSpec>;

Register BAUD writer

Aliased Type

pub struct W { /* private fields */ }

Implementations

impl W

pub fn sbr(&mut self) -> SbrW<'_, BaudSpec>

Bits 0:12 - Baud Rate Modulo Divisor.

pub fn sbns(&mut self) -> SbnsW<'_, BaudSpec>

Bit 13 - Stop Bit Number Select

pub fn rxedgie(&mut self) -> RxedgieW<'_, BaudSpec>

Bit 14 - RX Input Active Edge Interrupt Enable

pub fn lbkdie(&mut self) -> LbkdieW<'_, BaudSpec>

Bit 15 - LIN Break Detect Interrupt Enable

pub fn resyncdis(&mut self) -> ResyncdisW<'_, BaudSpec>

Bit 16 - Resynchronization Disable

pub fn bothedge(&mut self) -> BothedgeW<'_, BaudSpec>

Bit 17 - Both Edge Sampling

pub fn matcfg(&mut self) -> MatcfgW<'_, BaudSpec>

Bits 18:19 - Match Configuration

pub fn ridmae(&mut self) -> RidmaeW<'_, BaudSpec>

Bit 20 - Receiver Idle DMA Enable

pub fn rdmae(&mut self) -> RdmaeW<'_, BaudSpec>

Bit 21 - Receiver Full DMA Enable

pub fn tdmae(&mut self) -> TdmaeW<'_, BaudSpec>

Bit 23 - Transmitter DMA Enable

pub fn osr(&mut self) -> OsrW<'_, BaudSpec>

Bits 24:28 - Oversampling Ratio

pub fn m10(&mut self) -> M10W<'_, BaudSpec>

Bit 29 - 10-bit Mode select

pub fn maen2(&mut self) -> Maen2W<'_, BaudSpec>

Bit 30 - Match Address Mode Enable 2

pub fn maen1(&mut self) -> Maen1W<'_, BaudSpec>

Bit 31 - Match Address Mode Enable 1