RegisterBlock

s32k142_pac::lpi2c0

Struct RegisterBlock 

#[repr(C)]
pub struct RegisterBlock {
Show 40 fields
    verid: Verid,
    param: Param,
    _reserved2: [u8; 8],
    mcr: Mcr,
    msr: Msr,
    mier: Mier,
    mder: Mder,
    mcfgr0: Mcfgr0,
    mcfgr1: Mcfgr1,
    mcfgr2: Mcfgr2,
    mcfgr3: Mcfgr3,
    _reserved10: [u8; 16],
    mdmr: Mdmr,
    _reserved11: [u8; 4],
    mccr0: Mccr0,
    _reserved12: [u8; 4],
    mccr1: Mccr1,
    _reserved13: [u8; 4],
    mfcr: Mfcr,
    mfsr: Mfsr,
    mtdr: Mtdr,
    _reserved16: [u8; 12],
    mrdr: Mrdr,
    _reserved17: [u8; 156],
    scr: Scr,
    ssr: Ssr,
    sier: Sier,
    sder: Sder,
    _reserved21: [u8; 4],
    scfgr1: Scfgr1,
    scfgr2: Scfgr2,
    _reserved23: [u8; 20],
    samr: Samr,
    _reserved24: [u8; 12],
    sasr: Sasr,
    star: Star,
    _reserved26: [u8; 8],
    stdr: Stdr,
    _reserved27: [u8; 12],
    srdr: Srdr,

}
Expand description

Register block

Fields§

§verid: Verid§param: Param§_reserved2: [u8; 8]§mcr: Mcr§msr: Msr§mier: Mier§mder: Mder§mcfgr0: Mcfgr0§mcfgr1: Mcfgr1§mcfgr2: Mcfgr2§mcfgr3: Mcfgr3§_reserved10: [u8; 16]§mdmr: Mdmr§_reserved11: [u8; 4]§mccr0: Mccr0§_reserved12: [u8; 4]§mccr1: Mccr1§_reserved13: [u8; 4]§mfcr: Mfcr§mfsr: Mfsr§mtdr: Mtdr§_reserved16: [u8; 12]§mrdr: Mrdr§_reserved17: [u8; 156]§scr: Scr§ssr: Ssr§sier: Sier§sder: Sder§_reserved21: [u8; 4]§scfgr1: Scfgr1§scfgr2: Scfgr2§_reserved23: [u8; 20]§samr: Samr§_reserved24: [u8; 12]§sasr: Sasr§star: Star§_reserved26: [u8; 8]§stdr: Stdr§_reserved27: [u8; 12]§srdr: Srdr

Implementations§

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impl RegisterBlock

pub const fn verid(&self) -> &Verid

0x00 - Version ID Register

pub const fn param(&self) -> &Param

0x04 - Parameter Register

pub const fn mcr(&self) -> &Mcr

0x10 - Master Control Register

pub const fn msr(&self) -> &Msr

0x14 - Master Status Register

pub const fn mier(&self) -> &Mier

0x18 - Master Interrupt Enable Register

pub const fn mder(&self) -> &Mder

0x1c - Master DMA Enable Register

pub const fn mcfgr0(&self) -> &Mcfgr0

0x20 - Master Configuration Register 0

pub const fn mcfgr1(&self) -> &Mcfgr1

0x24 - Master Configuration Register 1

pub const fn mcfgr2(&self) -> &Mcfgr2

0x28 - Master Configuration Register 2

pub const fn mcfgr3(&self) -> &Mcfgr3

0x2c - Master Configuration Register 3

pub const fn mdmr(&self) -> &Mdmr

0x40 - Master Data Match Register

pub const fn mccr0(&self) -> &Mccr0

0x48 - Master Clock Configuration Register 0

pub const fn mccr1(&self) -> &Mccr1

0x50 - Master Clock Configuration Register 1

pub const fn mfcr(&self) -> &Mfcr

0x58 - Master FIFO Control Register

pub const fn mfsr(&self) -> &Mfsr

0x5c - Master FIFO Status Register

pub const fn mtdr(&self) -> &Mtdr

0x60 - Master Transmit Data Register

pub const fn mrdr(&self) -> &Mrdr

0x70 - Master Receive Data Register

pub const fn scr(&self) -> &Scr

0x110 - Slave Control Register

pub const fn ssr(&self) -> &Ssr

0x114 - Slave Status Register

pub const fn sier(&self) -> &Sier

0x118 - Slave Interrupt Enable Register

pub const fn sder(&self) -> &Sder

0x11c - Slave DMA Enable Register

pub const fn scfgr1(&self) -> &Scfgr1

0x124 - Slave Configuration Register 1

pub const fn scfgr2(&self) -> &Scfgr2

0x128 - Slave Configuration Register 2

pub const fn samr(&self) -> &Samr

0x140 - Slave Address Match Register

pub const fn sasr(&self) -> &Sasr

0x150 - Slave Address Status Register

pub const fn star(&self) -> &Star

0x154 - Slave Transmit ACK Register

pub const fn stdr(&self) -> &Stdr

0x160 - Slave Transmit Data Register

pub const fn srdr(&self) -> &Srdr

0x170 - Slave Receive Data Register

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