RegisterBlock

s32k146_pac::pdb0

Struct RegisterBlock 

#[repr(C)]
pub struct RegisterBlock {
Show 36 fields
    sc: Sc,
    mod_: Mod,
    cnt: Cnt,
    idly: Idly,
    chc1: (),
    _reserved5: [u8; 4],
    chs: (),
    _reserved6: [u8; 4],
    chdly0: (),
    _reserved7: [u8; 4],
    ch0dly1: Ch0dly1,
    ch0dly2: Ch0dly2,
    ch0dly3: Ch0dly3,
    ch0dly4: Ch0dly4,
    ch0dly5: Ch0dly5,
    ch0dly6: Ch0dly6,
    ch0dly7: Ch0dly7,
    _reserved14: [u8; 12],
    ch1dly1: Ch0dly1,
    ch1dly2: Ch0dly2,
    ch1dly3: Ch0dly3,
    ch1dly4: Ch0dly4,
    ch1dly5: Ch0dly5,
    ch1dly6: Ch0dly6,
    ch1dly7: Ch0dly7,
    _reserved21: [u8; 12],
    ch2dly1: Ch0dly1,
    ch2dly2: Ch0dly2,
    ch2dly3: Ch0dly3,
    ch2dly4: Ch0dly4,
    ch2dly5: Ch0dly5,
    ch2dly6: Ch0dly6,
    ch2dly7: Ch0dly7,
    _reserved28: [u8; 264],
    poen: Poen,
    _reserved_29_dly1: [u8; 4],

}
Expand description

Register block

Fields§

§sc: Sc§mod_: Mod§cnt: Cnt§idly: Idly§chc1: ()§_reserved5: [u8; 4]§chs: ()§_reserved6: [u8; 4]§chdly0: ()§_reserved7: [u8; 4]§ch0dly1: Ch0dly1§ch0dly2: Ch0dly2§ch0dly3: Ch0dly3§ch0dly4: Ch0dly4§ch0dly5: Ch0dly5§ch0dly6: Ch0dly6§ch0dly7: Ch0dly7§_reserved14: [u8; 12]§ch1dly1: Ch0dly1§ch1dly2: Ch0dly2§ch1dly3: Ch0dly3§ch1dly4: Ch0dly4§ch1dly5: Ch0dly5§ch1dly6: Ch0dly6§ch1dly7: Ch0dly7§_reserved21: [u8; 12]§ch2dly1: Ch0dly1§ch2dly2: Ch0dly2§ch2dly3: Ch0dly3§ch2dly4: Ch0dly4§ch2dly5: Ch0dly5§ch2dly6: Ch0dly6§ch2dly7: Ch0dly7§_reserved28: [u8; 264]§poen: Poen§_reserved_29_dly1: [u8; 4]

Implementations§

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impl RegisterBlock

pub const fn sc(&self) -> &Sc

0x00 - Status and Control register

pub const fn mod_(&self) -> &Mod

0x04 - Modulus register

pub const fn cnt(&self) -> &Cnt

0x08 - Counter register

pub const fn idly(&self) -> &Idly

0x0c - Interrupt Delay register

pub const fn chc1(&self, n: usize) -> &Chc1

0x10..0x1c - Channel n Control register 1

pub fn chc1_iter(&self) -> impl Iterator<Item = &Chc1>

Iterator for array of: 0x10..0x1c - Channel n Control register 1

pub const fn ch0c1(&self) -> &Chc1

0x10 - Channel n Control register 1

pub const fn ch1c1(&self) -> &Chc1

0x38 - Channel n Control register 1

pub const fn ch2c1(&self) -> &Chc1

0x60 - Channel n Control register 1

pub const fn chs(&self, n: usize) -> &Chs

0x14..0x20 - Channel n Status register

pub fn chs_iter(&self) -> impl Iterator<Item = &Chs>

Iterator for array of: 0x14..0x20 - Channel n Status register

pub const fn ch0s(&self) -> &Chs

0x14 - Channel n Status register

pub const fn ch1s(&self) -> &Chs

0x3c - Channel n Status register

pub const fn ch2s(&self) -> &Chs

0x64 - Channel n Status register

pub const fn chdly0(&self, n: usize) -> &Chdly0

0x18..0x24 - Channel n Delay 0 register

pub fn chdly0_iter(&self) -> impl Iterator<Item = &Chdly0>

Iterator for array of: 0x18..0x24 - Channel n Delay 0 register

pub const fn ch0dly0(&self) -> &Chdly0

0x18 - Channel n Delay 0 register

pub const fn ch1dly0(&self) -> &Chdly0

0x40 - Channel n Delay 0 register

pub const fn ch2dly0(&self) -> &Chdly0

0x68 - Channel n Delay 0 register

pub const fn ch0dly1(&self) -> &Ch0dly1

0x1c - Channel n Delay 1 register

pub const fn ch0dly2(&self) -> &Ch0dly2

0x20 - Channel n Delay 2 register

pub const fn ch0dly3(&self) -> &Ch0dly3

0x24 - Channel n Delay 3 register

pub const fn ch0dly4(&self) -> &Ch0dly4

0x28 - Channel n Delay 4 register

pub const fn ch0dly5(&self) -> &Ch0dly5

0x2c - Channel n Delay 5 register

pub const fn ch0dly6(&self) -> &Ch0dly6

0x30 - Channel n Delay 6 register

pub const fn ch0dly7(&self) -> &Ch0dly7

0x34 - Channel n Delay 7 register

pub const fn ch1dly1(&self) -> &Ch0dly1

0x1c - Channel n Delay 1 register

pub const fn ch1dly2(&self) -> &Ch0dly2

0x20 - Channel n Delay 2 register

pub const fn ch1dly3(&self) -> &Ch0dly3

0x24 - Channel n Delay 3 register

pub const fn ch1dly4(&self) -> &Ch0dly4

0x28 - Channel n Delay 4 register

pub const fn ch1dly5(&self) -> &Ch0dly5

0x2c - Channel n Delay 5 register

pub const fn ch1dly6(&self) -> &Ch0dly6

0x30 - Channel n Delay 6 register

pub const fn ch1dly7(&self) -> &Ch0dly7

0x34 - Channel n Delay 7 register

pub const fn ch2dly1(&self) -> &Ch0dly1

0x1c - Channel n Delay 1 register

pub const fn ch2dly2(&self) -> &Ch0dly2

0x20 - Channel n Delay 2 register

pub const fn ch2dly3(&self) -> &Ch0dly3

0x24 - Channel n Delay 3 register

pub const fn ch2dly4(&self) -> &Ch0dly4

0x28 - Channel n Delay 4 register

pub const fn ch2dly5(&self) -> &Ch0dly5

0x2c - Channel n Delay 5 register

pub const fn ch2dly6(&self) -> &Ch0dly6

0x30 - Channel n Delay 6 register

pub const fn ch2dly7(&self) -> &Ch0dly7

0x34 - Channel n Delay 7 register

pub const fn poen(&self) -> &Poen

0x190 - Pulse-Out n Enable register

pub const fn dly2(&self) -> &Dly2

0x194 - PDB0_DLY2 register.

pub const fn podly(&self) -> &Podly

0x194 - Pulse-Out n Delay register

pub const fn dly1(&self) -> &Dly1

0x196 - PDB0_DLY1 register.

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