Type Alias PrescaleW 

pub type PrescaleW<'a, REG> = FieldWriter<'a, REG, 4, Prescale, Safe>;

Field PRESCALE writer - Prescale Value

Aliased Type

pub struct PrescaleW<'a, REG> { /* private fields */ }

Implementations

impl<'a, REG> PrescaleW<'a, REG>

where REG: Writable + RegisterSpec, REG::Ux: From<u8>,

pub fn _0000(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.

pub fn _0001(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.

pub fn _0010(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.

pub fn _0011(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.

pub fn _0100(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.

pub fn _0101(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.

pub fn _0110(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.

pub fn _0111(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.

pub fn _1000(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.

pub fn _1001(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.

pub fn _1010(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.

pub fn _1011(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.

pub fn _1100(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.

pub fn _1101(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.

pub fn _1110(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.

pub fn _1111(self) -> &'a mut W<REG>

Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.