Enum Interrupt 

#[repr(u16)]
pub enum Interrupt {
    DMA0 = 0,
    DMA1 = 1,
    DMA2 = 2,
    DMA3 = 3,
    DMA4 = 4,
    DMA5 = 5,
    DMA6 = 6,
    DMA7 = 7,
    DMA8 = 8,
    DMA9 = 9,
    DMA10 = 10,
    DMA11 = 11,
    DMA12 = 12,
    DMA13 = 13,
    DMA14 = 14,
    DMA15 = 15,
    DMA_Error = 16,
    MCM = 17,
    FTFC = 18,
    Read_Collision = 19,
    LVD_LVW = 20,
    FTFC_Fault = 21,
    WDOG_EWM = 22,
    RCM = 23,
    LPI2C0_Master = 24,
    LPI2C0_Slave = 25,
    LPSPI0 = 26,
    LPSPI1 = 27,
    LPSPI2 = 28,
    LPUART0_RxTx = 31,
    LPUART1_RxTx = 33,
    LPUART2_RxTx = 35,
    ADC0 = 39,
    ADC1 = 40,
    CMP0 = 41,
    ERM_single_fault = 44,
    ERM_double_fault = 45,
    RTC = 46,
    RTC_Seconds = 47,
    LPIT0_Ch0 = 48,
    LPIT0_Ch1 = 49,
    LPIT0_Ch2 = 50,
    LPIT0_Ch3 = 51,
    PDB0 = 52,
    SCG = 57,
    LPTMR0 = 58,
    PORTA = 59,
    PORTB = 60,
    PORTC = 61,
    PORTD = 62,
    PORTE = 63,
    SWI = 64,
    PDB1 = 68,
    FLEXIO = 69,
    CAN0_ORed = 78,
    CAN0_Error = 79,
    CAN0_Wake_Up = 80,
    CAN0_ORed_0_15_MB = 81,
    CAN0_ORed_16_31_MB = 82,
    CAN1_ORed = 85,
    CAN1_Error = 86,
    CAN1_ORed_0_15_MB = 88,
    CAN1_ORed_16_31_MB = 89,
    CAN2_ORed = 92,
    CAN2_Error = 93,
    CAN2_ORed_0_15_MB = 95,
    FTM0_Ch0_Ch1 = 99,
    FTM0_Ch2_Ch3 = 100,
    FTM0_Ch4_Ch5 = 101,
    FTM0_Ch6_Ch7 = 102,
    FTM0_Fault = 103,
    FTM0_Ovf_Reload = 104,
    FTM1_Ch0_Ch1 = 105,
    FTM1_Ch2_Ch3 = 106,
    FTM1_Ch4_Ch5 = 107,
    FTM1_Ch6_Ch7 = 108,
    FTM1_Fault = 109,
    FTM1_Ovf_Reload = 110,
    FTM2_Ch0_Ch1 = 111,
    FTM2_Ch2_Ch3 = 112,
    FTM2_Ch4_Ch5 = 113,
    FTM2_Ch6_Ch7 = 114,
    FTM2_Fault = 115,
    FTM2_Ovf_Reload = 116,
    FTM3_Ch0_Ch1 = 117,
    FTM3_Ch2_Ch3 = 118,
    FTM3_Ch4_Ch5 = 119,
    FTM3_Ch6_Ch7 = 120,
    FTM3_Fault = 121,
    FTM3_Ovf_Reload = 122,
    FTM4_Ch0_Ch1 = 123,
    FTM4_Ch2_Ch3 = 124,
    FTM4_Ch4_Ch5 = 125,
    FTM4_Ch6_Ch7 = 126,
    FTM4_Fault = 127,
    FTM4_Ovf_Reload = 128,
    FTM5_Ch0_Ch1 = 129,
    FTM5_Ch2_Ch3 = 130,
    FTM5_Ch4_Ch5 = 131,
    FTM5_Ch6_Ch7 = 132,
    FTM5_Fault = 133,
    FTM5_Ovf_Reload = 134,
}

Enumeration of all the interrupts.

Variants

DMA0 = 0

0 - DMA0

DMA1 = 1

1 - DMA1

DMA2 = 2

2 - DMA2

DMA3 = 3

3 - DMA3

DMA4 = 4

4 - DMA4

DMA5 = 5

5 - DMA5

DMA6 = 6

6 - DMA6

DMA7 = 7

7 - DMA7

DMA8 = 8

8 - DMA8

DMA9 = 9

9 - DMA9

DMA10 = 10

10 - DMA10

DMA11 = 11

11 - DMA11

DMA12 = 12

12 - DMA12

DMA13 = 13

13 - DMA13

DMA14 = 14

14 - DMA14

DMA15 = 15

15 - DMA15

DMA_Error = 16

16 - DMA_Error

MCM = 17

17 - MCM

FTFC = 18

18 - FTFC

Read_Collision = 19

19 - Read_Collision

LVD_LVW = 20

20 - LVD_LVW

FTFC_Fault = 21

21 - FTFC_Fault

WDOG_EWM = 22

22 - WDOG_EWM

RCM = 23

23 - RCM

LPI2C0_Master = 24

24 - LPI2C0_Master

LPI2C0_Slave = 25

25 - LPI2C0_Slave

LPSPI0 = 26

26 - LPSPI0

LPSPI1 = 27

27 - LPSPI1

LPSPI2 = 28

28 - LPSPI2

LPUART0_RxTx = 31

31 - LPUART0_RxTx

LPUART1_RxTx = 33

33 - LPUART1_RxTx

LPUART2_RxTx = 35

35 - LPUART2_RxTx

ADC0 = 39

39 - ADC0

ADC1 = 40

40 - ADC1

CMP0 = 41

41 - CMP0

ERM_single_fault = 44

44 - ERM_single_fault

ERM_double_fault = 45

45 - ERM_double_fault

RTC = 46

46 - RTC

RTC_Seconds = 47

47 - RTC_Seconds

LPIT0_Ch0 = 48

48 - LPIT0_Ch0

LPIT0_Ch1 = 49

49 - LPIT0_Ch1

LPIT0_Ch2 = 50

50 - LPIT0_Ch2

LPIT0_Ch3 = 51

51 - LPIT0_Ch3

PDB0 = 52

52 - PDB0

SCG = 57

57 - SCG

LPTMR0 = 58

58 - LPTMR0

PORTA = 59

59 - PORTA

PORTB = 60

60 - PORTB

PORTC = 61

61 - PORTC

PORTD = 62

62 - PORTD

PORTE = 63

63 - PORTE

SWI = 64

64 - SWI

PDB1 = 68

68 - PDB1

FLEXIO = 69

69 - FLEXIO

CAN0_ORed = 78

78 - CAN0_ORed

CAN0_Error = 79

79 - CAN0_Error

CAN0_Wake_Up = 80

80 - CAN0_Wake_Up

CAN0_ORed_0_15_MB = 81

81 - CAN0_ORed_0_15_MB

CAN0_ORed_16_31_MB = 82

82 - CAN0_ORed_16_31_MB

CAN1_ORed = 85

85 - CAN1_ORed

CAN1_Error = 86

86 - CAN1_Error

CAN1_ORed_0_15_MB = 88

88 - CAN1_ORed_0_15_MB

CAN1_ORed_16_31_MB = 89

89 - CAN1_ORed_16_31_MB

CAN2_ORed = 92

92 - CAN2_ORed

CAN2_Error = 93

93 - CAN2_Error

CAN2_ORed_0_15_MB = 95

95 - CAN2_ORed_0_15_MB

FTM0_Ch0_Ch1 = 99

99 - FTM0_Ch0_Ch1

FTM0_Ch2_Ch3 = 100

100 - FTM0_Ch2_Ch3

FTM0_Ch4_Ch5 = 101

101 - FTM0_Ch4_Ch5

FTM0_Ch6_Ch7 = 102

102 - FTM0_Ch6_Ch7

FTM0_Fault = 103

103 - FTM0_Fault

FTM0_Ovf_Reload = 104

104 - FTM0_Ovf_Reload

FTM1_Ch0_Ch1 = 105

105 - FTM1_Ch0_Ch1

FTM1_Ch2_Ch3 = 106

106 - FTM1_Ch2_Ch3

FTM1_Ch4_Ch5 = 107

107 - FTM1_Ch4_Ch5

FTM1_Ch6_Ch7 = 108

108 - FTM1_Ch6_Ch7

FTM1_Fault = 109

109 - FTM1_Fault

FTM1_Ovf_Reload = 110

110 - FTM1_Ovf_Reload

FTM2_Ch0_Ch1 = 111

111 - FTM2_Ch0_Ch1

FTM2_Ch2_Ch3 = 112

112 - FTM2_Ch2_Ch3

FTM2_Ch4_Ch5 = 113

113 - FTM2_Ch4_Ch5

FTM2_Ch6_Ch7 = 114

114 - FTM2_Ch6_Ch7

FTM2_Fault = 115

115 - FTM2_Fault

FTM2_Ovf_Reload = 116

116 - FTM2_Ovf_Reload

FTM3_Ch0_Ch1 = 117

117 - FTM3_Ch0_Ch1

FTM3_Ch2_Ch3 = 118

118 - FTM3_Ch2_Ch3

FTM3_Ch4_Ch5 = 119

119 - FTM3_Ch4_Ch5

FTM3_Ch6_Ch7 = 120

120 - FTM3_Ch6_Ch7

FTM3_Fault = 121

121 - FTM3_Fault

FTM3_Ovf_Reload = 122

122 - FTM3_Ovf_Reload

FTM4_Ch0_Ch1 = 123

123 - FTM4_Ch0_Ch1

FTM4_Ch2_Ch3 = 124

124 - FTM4_Ch2_Ch3

FTM4_Ch4_Ch5 = 125

125 - FTM4_Ch4_Ch5

FTM4_Ch6_Ch7 = 126

126 - FTM4_Ch6_Ch7

FTM4_Fault = 127

127 - FTM4_Fault

FTM4_Ovf_Reload = 128

128 - FTM4_Ovf_Reload

FTM5_Ch0_Ch1 = 129

129 - FTM5_Ch0_Ch1

FTM5_Ch2_Ch3 = 130

130 - FTM5_Ch2_Ch3

FTM5_Ch4_Ch5 = 131

131 - FTM5_Ch4_Ch5

FTM5_Ch6_Ch7 = 132

132 - FTM5_Ch6_Ch7

FTM5_Fault = 133

133 - FTM5_Fault

FTM5_Ovf_Reload = 134

134 - FTM5_Ovf_Reload

Trait Implementations

impl Clone for Interrupt

fn clone(&self) -> Interrupt

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Interrupt

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Format for Interrupt

fn format(&self, f: Formatter<'_>)

Writes the defmt representation of self to fmt.

impl InterruptNumber for Interrupt

fn number(self) -> u16

Return the interrupt number associated with this variant.

impl PartialEq for Interrupt

fn eq(&self, other: &Interrupt) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Interrupt

impl Eq for Interrupt

impl StructuralPartialEq for Interrupt