Module cfg1 

ADC Configuration Register 1

Structs

Cfg1Spec

ADC Configuration Register 1

Enums

Adiclk

Input Clock Select

Adiv

Clock Divide Select

Mode

Conversion mode selection

Type Aliases

AdiclkR

Field ADICLK reader - Input Clock Select

AdiclkW

Field ADICLK writer - Input Clock Select

AdivR

Field ADIV reader - Clock Divide Select

AdivW

Field ADIV writer - Clock Divide Select

ClrltrgW

Field CLRLTRG writer - Clear Latch Trigger in Trigger Handler Block

ModeR

Field MODE reader - Conversion mode selection

ModeW

Field MODE writer - Conversion mode selection

R

Register CFG1 reader

W

Register CFG1 writer