Module ccr 

Configuration and Control Register

Structs

CcrSpec

Configuration and Control Register

Enums

Bfhfnmign

Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.

Div0Trp

Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0

Nonbasethrdena

Indicates how the processor enters Thread mode

Stkalign

Indicates stack alignment on exception entry

UnalignTrp

Enables unaligned access traps

Usersetmpend

Enables unprivileged software access to the STIR

Type Aliases

BfhfnmignR

Field BFHFNMIGN reader - Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.

BfhfnmignW

Field BFHFNMIGN writer - Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.

Div0TrpR

Field DIV_0_TRP reader - Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0

Div0TrpW

Field DIV_0_TRP writer - Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0

NonbasethrdenaR

Field NONBASETHRDENA reader - Indicates how the processor enters Thread mode

NonbasethrdenaW

Field NONBASETHRDENA writer - Indicates how the processor enters Thread mode

R

Register CCR reader

StkalignR

Field STKALIGN reader - Indicates stack alignment on exception entry

StkalignW

Field STKALIGN writer - Indicates stack alignment on exception entry

UnalignTrpR

Field UNALIGN_TRP reader - Enables unaligned access traps

UnalignTrpW

Field UNALIGN_TRP writer - Enables unaligned access traps

UsersetmpendR

Field USERSETMPEND reader - Enables unprivileged software access to the STIR

UsersetmpendW

Field USERSETMPEND writer - Enables unprivileged software access to the STIR

W

Register CCR writer