Module sim
Expand description
System Integration Module
Modules§
- adcopt
- ADC Options Register
- chipctl
- Chip Control register
- clkdiv4
- System Clock Divider Register 4
- fcfg1
- Flash Configuration Register 1
- ftmopt0
- FTM Option Register 0
- ftmopt1
- FTM Option Register 1
- lpoclks
- LPO Clock Select Register
- misctrl0
- Miscellaneous control register 0
- misctrl1
- Miscellaneous Control register 1
- platcgc
- Platform Clock Gating Control Register
- sdid
- System Device Identification Register
- uidh
- Unique Identification Register High
- uidl
- Unique Identification Register Low
- uidmh
- Unique Identification Register Mid-High
- uidml
- Unique Identification Register Mid Low
Structs§
- Register
Block - Register block
Type Aliases§
- Adcopt
- ADCOPT (rw) register accessor: ADC Options Register
- Chipctl
- CHIPCTL (rw) register accessor: Chip Control register
- Clkdiv4
- CLKDIV4 (rw) register accessor: System Clock Divider Register 4
- Fcfg1
- FCFG1 (rw) register accessor: Flash Configuration Register 1
- Ftmopt0
- FTMOPT0 (rw) register accessor: FTM Option Register 0
- Ftmopt1
- FTMOPT1 (rw) register accessor: FTM Option Register 1
- Lpoclks
- LPOCLKS (rw) register accessor: LPO Clock Select Register
- Misctrl0
- MISCTRL0 (rw) register accessor: Miscellaneous control register 0
- Misctrl1
- MISCTRL1 (rw) register accessor: Miscellaneous Control register 1
- Platcgc
- PLATCGC (rw) register accessor: Platform Clock Gating Control Register
- Sdid
- SDID (r) register accessor: System Device Identification Register
- Uidh
- UIDH (r) register accessor: Unique Identification Register High
- Uidl
- UIDL (r) register accessor: Unique Identification Register Low
- Uidmh
- UIDMH (r) register accessor: Unique Identification Register Mid-High
- Uidml
- UIDML (r) register accessor: Unique Identification Register Mid Low