Module lpi2c0 

The LPI2C Memory Map/Register Definition can be found here.

Re-exports

pub use Mccr0 as Mccr1;

pub use mccr0 as mccr1;

Modules

mccr0

Master Clock Configuration Register 0

mcfgr0

Master Configuration Register 0

mcfgr1

Master Configuration Register 1

mcfgr2

Master Configuration Register 2

mcfgr3

Master Configuration Register 3

mcr

Master Control Register

mder

Master DMA Enable Register

mdmr

Master Data Match Register

mfcr

Master FIFO Control Register

mfsr

Master FIFO Status Register

mier

Master Interrupt Enable Register

mrdr

Master Receive Data Register

msr

Master Status Register

mtdr

Master Transmit Data Register

param

Parameter Register

samr

Slave Address Match Register

sasr

Slave Address Status Register

scfgr1

Slave Configuration Register 1

scfgr2

Slave Configuration Register 2

scr

Slave Control Register

sder

Slave DMA Enable Register

sier

Slave Interrupt Enable Register

srdr

Slave Receive Data Register

ssr

Slave Status Register

star

Slave Transmit ACK Register

stdr

Slave Transmit Data Register

verid

Version ID Register

Structs

RegisterBlock

Register block

Type Aliases

Mccr0

MCCR0 (rw) register accessor: Master Clock Configuration Register 0

Mcfgr0

MCFGR0 (rw) register accessor: Master Configuration Register 0

Mcfgr1

MCFGR1 (rw) register accessor: Master Configuration Register 1

Mcfgr2

MCFGR2 (rw) register accessor: Master Configuration Register 2

Mcfgr3

MCFGR3 (rw) register accessor: Master Configuration Register 3

Mcr

MCR (rw) register accessor: Master Control Register

Mder

MDER (rw) register accessor: Master DMA Enable Register

Mdmr

MDMR (rw) register accessor: Master Data Match Register

Mfcr

MFCR (rw) register accessor: Master FIFO Control Register

Mfsr

MFSR (r) register accessor: Master FIFO Status Register

Mier

MIER (rw) register accessor: Master Interrupt Enable Register

Mrdr

MRDR (r) register accessor: Master Receive Data Register

Msr

MSR (rw) register accessor: Master Status Register

Mtdr

MTDR (rw) register accessor: Master Transmit Data Register

Param

PARAM (r) register accessor: Parameter Register

Samr

SAMR (rw) register accessor: Slave Address Match Register

Sasr

SASR (r) register accessor: Slave Address Status Register

Scfgr1

SCFGR1 (rw) register accessor: Slave Configuration Register 1

Scfgr2

SCFGR2 (rw) register accessor: Slave Configuration Register 2

Scr

SCR (rw) register accessor: Slave Control Register

Sder

SDER (rw) register accessor: Slave DMA Enable Register

Sier

SIER (rw) register accessor: Slave Interrupt Enable Register

Srdr

SRDR (r) register accessor: Slave Receive Data Register

Ssr

SSR (rw) register accessor: Slave Status Register

Star

STAR (rw) register accessor: Slave Transmit ACK Register

Stdr

STDR (rw) register accessor: Slave Transmit Data Register

Verid

VERID (r) register accessor: Version ID Register